The rate of adoption of technology continues to increase in different sectors of the global economy, including consumer, media and communications, industrial, medical, defense, agriculture, financial, and others to name a few. Many technology segments are still at their infancy phase by historic measures, with substantial growth opportunity ahead of them in such application as the internet, social media, virtual and augmented reality, hand-held electronics, smart-phones, internet of things, intelligent robotics (drones), factory automation, electro-medical equipment, electric and autonomous automobiles, crypto-currency, etc.
As a result of this dynamic and expanding technological foot-print globally, the appetite for chips with lower cost, higher performance, high density with more features in small chip area (for high integration), and requiring lower power consumption continues to rise. This dynamic has resulted not only in explosion of number of bits (digital data) but also in the need for higher speed of communication of the digital bits that can be accessible where and when needed.
For the last 40 years, semiconductor manufacturing has been advancing (in accordance with Moore's law predictions) by shrinking fabrication geometries and providing faster transistors with more interconnect layers between them, that has in turn enabled integrated circuits (IC or chips) to be made faster, smaller, denser, and at lower price. For example, there were transistors with channel lengths of 20 micro-meters (1/1000,000 meter) and one interconnect layer about 40 years ago, versus currently when there are 10 nano-meters (1/1000,000,000 meter) transistors that are about 20,000 times smaller and a dozen interconnect layers that can go between them.
The semiconductor manufacturing advancements have in the large part been responsible for delivering chips with fast processing speed, high density and increased levels of feature-function integrations, at declining prices in the last 3 decades that has facilitated technology's volume maximization and mass market adoption. During all this period, data was growing rapidly until the last decade when data growth began to accelerate in the advent of data hungry applications such as the internet and phone and voice-image-video transmissions and recognition, for example, which have currently become main stream and in the hands of consumers via mobile devices, globally.
The technology landscape is currently facing an imperfect storm, where Moore's law is coming to an end. Compared to the past 4 decades, the semiconductor manufacturing's ability is slowing in delivering more cost-power-performance improvements, because in the most part, transistors size reductions are at or near their physical limit at a few nanometers, and all the while the sheer volume of digital data explosion continues.
What has come to help us, in this imperfect storm, are Machine learning (ML) and Artificial Intelligence (AI).
While chip manufacturing has been approaching or nearly running out of steam to handle this data explosion, ML and AI software and digital circuit design methodology can help accelerate and automate some of the data processing at the edge of the network or closer to sensors with an aim to make sense, manage, and crunch this large amount of data before, for example, such massive unmanaged data volumes reach a central office for processing (and in a way, ML and AI act like a filter to zoom on data that matters and get rid of or ignore the rest).
It is likely that without AI and ML technology, the sunset phase of the Moore's law would slow the growth of emerging applications (that have massive amount of data) such as computer vision, data mining, economic and finance, biology, natural language processing, language translation, autonomous car, just to name a few.
AI and ML technologies and applications, although mostly at their infancy stage, could help manage and grow the present data explosion, with less disruption, and accordingly it could facilitate the growth of some of the emerging applications noted above.
However, the energy-inefficiency of purely digital computation chips remain a major concern and hurdle for AI and ML. The power consumption and cost of digital solutions for AI and ML may be excessive and may not fit the bill in some applications, especially at the edge, mobile products, or at sensor levels.
Thus, there could be greater demand for analog and mixed-signal signal processing and implementations, to aid AI and ML digital computations, and offer cost-performance advantages, especially near the edge or access or sensors or mobile gears (e.g., cell phone or robot, etc.) and closer to where and when data is gathered.
For example, while speed and precision of data processing may be most critical for AI and ML systems that are in the cloud and for scientific applications, as stated before, there are needs for AI and ML systems near the edge, access devices, or robotics, for example, where low power consumption and lower cost is most important, and moderate accuracy at lower speeds could be acceptable for the applications and not impractical. Utilization of analog and mixed signal processing (along with digital computation) can help such segments of AI and ML.
One of the aims of the present invention is to provide analog and mixed-mode multiplication solutions for AI and ML applications that require low power.
As it relates to AI and ML, one of the areas that the present invention is addressing is approximate computing where less than perfect precision would suffice. In this segment, analog and mixed-signal implementations can stand on their own to perform the needed computation or alternatively analog and mixed-signal computation solutions can reside in a hybrid computation platform where they can augment the digital computation. The basic premise here is to bargain power consumption and size for quality where decisions are made by examining the statistical attributes of the data.
The motivation to utilize analog (and mixed-signal) here is to harness the faculty of a single analog signal which has the capacity to transfer and or compute a plurality of digital signals in one time cycle and one power cycle, which has the potential for saving area, power (e.g., per computational bit), and cycle time (e.g., clock free asynchronous conversion) when performing a computation.
There are purely analog multiplier solutions applicable to ML and AI. Analog multipliers can operate with low power consumptions and offer low-to-middle precision at low-to-middle speeds. For low power applications, multipliers may be required to operate with one-volt or sub-one-volt power supplies, which renders conventional analog multipliers as impractical given their operating head room requirements. Integrating conventional analog multipliers in digital chip, that are generally noisy, may cause cross talk and hinder such analog multiplier performance.
In this disclosure, it will become clearer that an objective of the disclosed multiplier embodiments is to utilize data converters, including analog-to-digital converters (ADC) and digital-to-analog converters (DAC), in part because they can be ported to conventional digital CMOS manufacturing, and have a seamless interface with digital logic that make the software programmability easier.
Another objective of this disclosure is that performing the AI function using analog and mixed signal solutions versus purely digital solutions could help reduce the software instructions set, size of memory, and reduce the rate of interface between AI/ML engines and memory/data which can potentially lower dynamic power consumption and the total system cost for some applications.
Another objective is of this disclosure is that the data converter's reference networks can be programmed to approximate non-linear input-to-output transfer functions (e.g., logarithmic, square, etc.), which makes them suitable for approximate multipliers that can be utilized for approximate computation to save on power consumption and circuit cost. It is of note that the ability of efficient (low power, small area) analog or mixed signal computation deteriorates as the accuracy requirements increase, which is why the proposed invention would benefit the approximate computing, suitable in some segments in artificial intelligence applications with mid-range accuracy requirement.
Another objective of the disclosed invention is that plurality of multipliers (utilizing plurality of data-converters) that share the same reference network (or use copies of the same reference network) could lower power consumption, reduce chip area as well as improve matching between multipliers (via its data-converters) channels. This feature would provide system level flexibility, including cost effective or global trimming to improve system accuracy.
Another objective of this disclosure is that multipliers, utilizing data converters, are capable of operating free of clock (asynchronously), which is also required for some ML and AI applications. Moreover, clock free operations substantially reduce dynamic power consumption that is associated with computation chips that require always on clocks.
Another objective of the disclosed invention is that by retaining the accuracy, but reducing the resolution of data-converters disclosed here (e.g., a converter with 4-bits of resolution that is 8-bit accurate), generally would result in saving on chip area and lowering of power consumption. Accordingly, this invention discloses methods of disassembling the inputs signals before they are multiplied into segments with lower resolutions but retaining their accuracy. Then, performing the multiplication on the segments instead of the whole input signals, applying principles such as segmentation while utilizing a combination of purely digital functions and low-resolution data converters.
Another objective of the disclosed invention is that the mixed-mode and analog signal processing solutions whose zero-scale to full-scale dynamic ranges are not limited to high or low currents. For example, some analog signal processing units (e.g., multipliers) rely on operating transistors in the subthreshold regions which restricts the dynamic range of analog signal processing units (e.g., the multiplier) to low current. Also, some other analog signal processing units (e.g., multipliers) rely on operating transistors in the saturation regions which restricts the dynamic range of analog signal processing units (e.g., the multiplier) to higher current.
In summary, the objective of the disclosed invention suitable for ML and AI applications are to provide multipliers that (a) are compatible with main-stream digital CMOS manufacturing, (b) can operate with low power supplies, (c) can operate mixed-mode, enabling the multiplier to be seamlessly integrated on large digital chips, (d) are capable of utilizing approximate multiplication which can provide cost-performance advantages and greater degree of trade-off flexibility (e) can operate asynchronously (e) offer low power consumption which providing low-to-moderate speeds and moderate-to-high precision needed for some segments of the ML and AI.